Study of Properties of Weight-based Two-module Sum Codes in Concurrent Error-Detection Circuits Based on Boolean Signal Correction

The features of the application of two-module sum codes in the synthesis of self-checking digital devices are considered. It is shown that the use of two-module sum codes significantly expands the number of ways to synthesize concurrent error-detection circuit both according to the traditional structure with the addition of data vectors with test ones, and according to an alternative one based on the principle of Boolean signals correction. Previously unknown characteristics of error detection by two-module sum codes in the residue ring modulo M = 4 with a “half division” of data symbols into two subsets have been established. It is shown that the number of potential undetectable errors in the codewords of two-module sum codes is ten times greater than the number of undetectable errors that occur exclusively in the data symbols of codewords. It is advisable to use this feature in the synthesis of concurrent error-detection circuit based on the Boolean signals correction by selecting a group of outputs, the signals from which are corrected in the concurrent error-detection circuit. The rule of allocation of functionally independent groups of outputs of the diagnostic object is applied. A generalized algorithm for the synthesis of concurrent error-detection circuit based on the Boolean signal’s correction using two-module weight-based sum codes has been formed. The experiment shows that using two-module weight-based sum codes, it is possible to obtain less redundant self-checking devices than using classical approaches. The results obtained in the course of the study can be effectively used in the development of self-checking digital devices and computing systems.

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