Method of high-level microarchitecture design of neuromorphic processors based on explicit separation of computations from transaction flow

An original method and a prototype of the software toolbox for designing neuromorphic processors are presented. The method is based on a high-level description of the hardware with explicit (at the source code level) allocation of pipeline transaction flows circulating inside the hardware structure and separation of the computations performed in this case from the logic of dynamic scheduling and flow control. This approach allows flexible combination of data processing algorithms with up-to-date mechanisms for improving performance and energy consumption in the hardware microarchitecture, effective sharing of responsibilities in the development of complex hardware, and reuse of auto-configurable microarchitectural structures. A formalization of the transaction concept (in a given context), a hardware design route based on transactions, and an algorithm for synthesizing the RTL design of neuromorphic processors based on “transactional” descriptions are proposed. A prototype of the software toolbox for synthesizing processors built on a framework for software-controlled hardware generation is described. The application of the proposed method and CAD components is demonstrated using the example of the development of an original neuromorphic processor executing models of fully connected pulse neural networks. This development confirms the achievability of competitive hardware characteristics with a significant improvement in project manageability, code reuse, a reduction in the number of errors and the overall labor intensity of design.

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